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MCT heteroepitaxial 4 × 288 FPA

Identifieur interne : 000466 ( Russie/Analysis ); précédent : 000465; suivant : 000467

MCT heteroepitaxial 4 × 288 FPA

Auteurs : RBID : Pascal:04-0033021

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English descriptors

Abstract

4 x 288 heteroepitaxial mercury-cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28 x 25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (013) GaAs substrates with CdZnTe buffer layers and had cutoff wavelength λco 11.8 ± 0.15 μm at T = 78 K. To decrease the surface influence of carrier recombination processes the compositionally dependent layers with increase of Cd content both toward the surface and HgCdTe/CdZnTe boundary interface were grown. Silicon readouts with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure, to qualify readout integrated circuits on wafer level at T = 300 K, was worked out. The silicon readouts for 4 x 288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4 x 288 MCT n-p-junctions, the detectivity for several tested 4 x 288 arrays was within D*λ ≅ 9 × 1010-1.8 × 1011 cm Hz1/2/W for background temperature Tb = 295 K.

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Pascal:04-0033021

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<div type="abstract" xml:lang="en">4 x 288 heteroepitaxial mercury-cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28 x 25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (013) GaAs substrates with CdZnTe buffer layers and had cutoff wavelength λ
<sub>co</sub>
11.8 ± 0.15 μm at T = 78 K. To decrease the surface influence of carrier recombination processes the compositionally dependent layers with increase of Cd content both toward the surface and HgCdTe/CdZnTe boundary interface were grown. Silicon readouts with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure, to qualify readout integrated circuits on wafer level at T = 300 K, was worked out. The silicon readouts for 4 x 288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4 x 288 MCT n-p-junctions, the detectivity for several tested 4 x 288 arrays was within D*
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<sub>co</sub>
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